Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs
Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs
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DOI：
10.1109/tcpmt.2020.3011325
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发表时间：
2020-07
期刊：
影响因子：
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通讯作者：
Paul K. Jo;Sreejith Kochupurackal Rajan;Joe L. Gonzalez;M. Bakir
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文献类型：
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作者：
Paul K. Jo;Sreejith Kochupurackal Rajan;Joe L. Gonzalez;M. Bakir
本文探讨了一种称为异构互连拼接技术（HIST）的多片集成技术。HIST通过多高度和细间距可压缩微互连（cmi）提供2.5-D和3-D集成功能。利用ANSYS Workbench仿真软件对多高度、小间距cmi进行了优化仿真。为了演示所提出技术的关键特征，制作和组装了一个试验台：将具有多高度cmi（65和$35~\mu \text{m}$高度）的锚定芯片组装到具有表面嵌入式芯片（$52~\mu \text{m}$厚度）的基板上，并使用焊料凸点进行机械粘合。细间距cmi （$30\,\,\mu \text{m}\,\,\times 30\,\,\mu \text{m}$）也被制造和演示，以满足高性能计算系统对更高I/O密度不断增长的需求。报告了电阻表征结果以及互连的力学表征。
A polylithic integration technology called heterogeneous interconnect stitching technology (HIST) is explored in this article. HIST provides both 2.5-D and 3-D integration capabilities enabled by multi-height and fine-pitch compressible microinterconnects (CMIs). The ANSYS Workbench simulator is used to optimize and simulate the multi-height and fine-pitch CMIs. A testbed is fabricated and assembled in order to demonstrate the key features of the proposed technology: the assembly of an anchor chip with multi-height CMIs (65 and $35~\mu \text{m}$ in height) onto a substrate with a surface-embedded chip ( $52~\mu \text{m}$ in thickness) and mechanical bonding using solder bumps. Fine-pitch CMIs ( $30\,\,\mu \text{m}\,\,\times 30\,\,\mu \text{m}$ ) are also fabricated and demonstrated in order to meet an ever-growing need for higher I/O densities for high-performance computing systems. Electrical resistance characterization results are reported as well as the mechanical characterization of interconnects.