A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration
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DOI：
10.1109/mcsoc.2019.00012
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发表时间：
2019-10
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影响因子：
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通讯作者：
Hayate Okuhara;Ryosuke Kazami;H. Amano
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文献类型：
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作者：
Hayate Okuhara;Ryosuke Kazami;H. Amano
在这项工作中，我们提出了一种低开销的性能监视器，它可以利用延迟链来模拟目标系统的最大工作频率，从而实现有效的自适应电压控制。所提出的监视器可以完全由一般pdk提供的逻辑单元构建；因此，可以使用基于单元格的自动设计流来实现它。此外，互连延迟行为也可以通过利用自动路由的导线来模拟。为了验证我们的概念，所提出的监视器是用65纳米完全耗尽绝缘体上硅（FD-SOI）技术制造的。实际芯片实验表明，自动化版图设计能够实现合理的延时仿真能力。实际上，当仿真CNN加速器的最大工作频率时，所提出的SDM实现了性能跟踪误差的几个百分点。此外，它的电力开销只有几个百分点。
In this work, we present a low-overhead performance monitor which can emulate the maximum operational frequency of a target system by utilizing a delay chain so as to achieve efficient adaptive voltage control. The proposed monitor can be fully built by logic cells provided by general PDKs; thus, an automatic cell-based design flow can be used for its implementation. In addition, interconnect delay behaviors can also be imitated by exploiting wires which are automatically routed. In order to validate our concept, the proposed monitor is fabricated with a 65-nm Fully Depleted Silicon on Insulator (FD-SOI) technology. Real chip experiments reveal that the automated layout design can achieve the reasonable ability to delay emulation. Indeed, when the maximum operational frequency of a CNN accelerator is emulated, the proposed SDM achieved several percents of the performance tracking error. Also, its power overhead is only few percents.