Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
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DOI：
10.1109/tvlsi.2006.887833
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发表时间：
2006-12
影响因子：
2.8
通讯作者：
C. K. Teh;M. Hamada;T. Fujita;H. Hara;Nobuyuki Ikumi;Y. Oowaki
中科院分区：
文献类型：
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作者：
C. K. Teh;M. Hamada;T. Fujita;H. Hara;Nobuyuki Ikumi;Y. Oowaki
本文介绍了一类新的低功耗高性能触发器，即条件数据映射触发器(CDMFR)，它通过将输入映射到消除冗余内部转换的配置来降低其动态功耗。我们提出了两种分别具有差动结构和单端结构的CDMFF，并将它们与最先进的触发器进行了比较。结果表明，这两种CDMFF分别具有各自组中最好的功率延迟积。在功耗方面，在数据活跃度小于50%时，单端和差分CDMF的功耗最小，在数据活跃度为25%时，分别比条件捕获触发器低31%和26%的功耗。在性能方面，与传输门脉冲锁存器和改进型读出放大器触发器相比，CDMFF实现了较小的数据到输出延迟。在时序可靠性方面，CDMFF在脉冲触发器中具有最好的内部竞争抗扰性。通过与传输门触发器的比较，给出了一个版图后的实例研究。结果表明，在数据活跃度为25%的情况下，单端CDMFF的数据到输出延迟降低了34%，功耗降低了28%，尽管大小增加了34%
This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size