Fault Attacks Resistant AES Hardware Implementation
Fault Attacks Resistant AES Hardware Implementation
复制标题
抗故障攻击 AES 硬件实现
DOI：
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复制
发表时间：
2019
期刊：
影响因子：
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通讯作者：
M. Machhout
中科院分区：
文献类型：
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作者：
H. Mestiri;N. Benhadjyoussef;M. Machhout
对称密码算法，特别是高级加密标准（AES）的故障注入攻击的保护对于保证传输数据的安全性非常重要。提出了一种基于信息冗余的AES故障检测方案。我们分析了检测方案对故障注入攻击的鲁棒性。仿真故障攻击结果表明，该算法的故障覆盖率达到了71.43%.此外，原始的和受保护的AES硬件实现已经在Xilinx Virtex-5 FPGA上实现。我们确认，保护AES是非常有效的，同时保持频率开销非常低。
The protection of the symmetric cryptographic algorithm, specially the Advanced Encryption Standard (AES), against fault injection attacks is very inportant to guarantee the security of transmitted data. In this paper, we proposed a new fault detection scheme based information redundancy for the AES. We analysis the detection scheme robustness against the fault injection attacks. The simulation fault attacks results prove that the fault coverage reaches 71.43%. In addition, the original and the protected AES hardware implementation have been implemented on the Xilinx Virtex-5 FPGA. We confirm that the protected AES is very effective while keeping the frequency overhead very low.