Online clock routing in Xilinx FPGAs for high-performance and reliability
Online clock routing in Xilinx FPGAs for high-performance and reliability
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Xilinx FPGA 中的在线时钟路由可实现高性能和可靠性
DOI：
10.1109/ahs.2012.6268634
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
T. Arslan
中科院分区：
文献类型：
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作者：
X. Iturbe;K. Benkrid;Raul Torrego;Ali Ebrahim;T. Arslan
在本文中，我们报告了可重构系统的设计和实现，该系统利用 Xilinx Virtex-4 FPGA 中存在的区域时钟资源来提高性能，并首次增强可靠性。与以前的方法不同，我们的系统能够单独管理区域时钟缓冲区（BUFR），以调整交付给每个硬件任务的频率，并动态检测影响时钟树的故障并从中恢复。为此，我们提出了全局和区域时钟多路复用器，分别称为 GCMUX 和 RCMUX，允许在需要时切换到备用时钟资源。这些多路复用器基于 FPGA 的内部可编程互连点，从而实现零面积开销。
In this paper, we report the design and implementation of a reconfigurable system that exploits regional clocking resources that exist in Xilinx Virtex-4 FPGAs for increased performance and, for the first time, enhanced reliability. Unlike previous approaches, our system is able to individually manage the regional clock buffers (BUFRs) to adjust the frequency delivered to each hardware task and to detect and recover from faults affecting the clock-tree on-the-fly. Towards this end, we propose global and regional clock multiplexers, named GCMUX and RCMUX respectively, which allow for switching to spare clocking resources whenever needed. These multiplexers are based on the inner programmable interconnection points of the FPGA, leading to zero area overheads.