SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs
SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs
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SuSy：用于在 FPGA 上高效构建高性能脉动阵列的编程模型
DOI：
10.1145/3400302.3415644
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发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Liang, Yun
中科院分区：
文献类型：
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作者：
Lai, Yi-Hsiang;Rong, Hongbo;Zheng, Size;Zhang, Weihao;Cui, Xiuping;Jia, Yunshan;Wang, Jie;Sullivan, Brendan;Zhang, Zhiru;Liang, Yun
脉动算法是FPGA和CGRA等空间结构中的杀手级应用之一。然而，对于给定的算法，使用传统的基于RTL的方法来设计和实现高性能的脉动阵列需要大量的人力。另一方面，现有的高级综合(HLS)工具要么(1)迫使程序员进行微编码，其中必须通过繁琐的代码重组和插入供应商特定的编译指示来执行太多的优化，要么(2)给予程序员太少的控制而不能影响按钮编译流程以获得高质量的结果。为了应对这些挑战，我们引入了Susy，一个由领域特定语言(DSL)和编译流程组成的编程框架，使程序员能够在FPGA上高效地构建高性能脉动阵列。使用Susy，程序员以统一递归方程(URS)的形式表达设计功能，只要底层计算具有统一的依赖结构，它就可以描述来自广泛应用的算法。Susy中的URE描述后面是一组分离的空间映射原语，这些原语指定如何将等式映射到空间体系结构。更具体地说，程序员可以应用时空变换和其他几种内存和I/O优化来高效地构建高效的脉动体系结构。实验结果表明，Susy能够用urs描述各种算法，并通过空间优化生成高性能的脉动阵列。例如，用Susy编写的SGEMM基准测试可以接近专家优化的手动设计的性能，同时使用的代码行减少了30倍。
Systolic algorithms are one of the killer applications on spatial architectures such as FPGAs and CGRAs. However, it requires a tremendous amount of human effort to design and implement a high-performance systolic array for a given algorithm using the traditional RTL-based methodology. On the other hand, existing high-level synthesis (HLS) tools either (1) force the programmers to do "micro-coding" where too many optimizations must be carried out through tedious code restructuring and insertion of vendor-specific pragmas, or (2) give them too little control to influence a push-button compilation flow to achieve high quality of results.To tackle these challenges, we introduce SuSy, a programming framework composed of a domain-specific language (DSL) and a compilation flow that enables programmers to productively build high-performance systolic arrays on FPGAs. With SuSy, programmers express the design functionality in the form of uniform recurrence equations (UREs), which can describe algorithms from a wide spectrum of applications as long as the underlying computation has a uniform dependence structure. The URE description in SuSy is followed by a set of decoupled spatial mapping primitives that specify how to map the equations to a spatial architecture. More concretely, programmers can apply space-time transformations and several other memory and I/O optimizations to build a highly efficient systolic architecture productively. Experimental results show that SuSy can describe various algorithms with UREs and generate high-performance systolic arrays by spatial optimizations. For instance, the SGEMM benchmark written in SuSy can approach the performance of the manual design optimized by experts, while using 30× fewer lines of code.