Design of a Logic-in-Memory Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme
Design of a Logic-in-Memory Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme
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基于位串行包数据传输方案的内存逻辑可重构VLSI设计
DOI：
10.1109/ismvl.2014.45
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
Michitaka Kameyama and Yoshichika Fujioka
中科院分区：
文献类型：
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作者：
Shintaro Harada;Xu Bai;Michitaka Kameyama and Yoshichika Fujioka
提出了一种新的分组数据传输方案(PDTS)，以减小基于存储器中逻辑结构的多值动态可重构VLSI的配置/控制存储器(CCM)大小。在PDTS中，用于存储器访问的CCM大小不是与可重构VLSI中的分布式存储器模块的数量成比例，而是与所有存储器中的读取操作的数量成比例。因此，与传统控制方案相比，可以实现显著减小CCM尺寸。此外，利用指示数据有效或无效的标志信息，PDTS有助于对差分对电路(DPC)中的电流源进行细粒度的开/关控制。
A new packet data transfer scheme (PDTS) is introduced to reduce a configuration/control memory (CCM) size of a multiple-valued dynamic reconfigurable VLSI based on a logic-in-memory architecture. In the PDTS, the CCM size for memory access is proportional not to the number of distributed memory modules in the reconfigurable VLSI, but to the number of read operations in all the memories. Thus, remarkable reduction of the CCM size can be achieved in comparison with the conventional control scheme. Moreover, the PDTS contributes to fine-grain ON/OFF control of the current sources in Differential-Pair Circuits (DPCs) utilizing flag information which indicates whether the data is valid or invalid.