Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology
Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology
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多阈值空约定逻辑 (MTNCL)：一种超低功耗异步电路设计方法
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
Jia Di
中科院分区：
文献类型：
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作者：
Liang Zhou;R. Parameswaran;F. A. Parsan;Scott C. Smith;Jia Di
本文提出了一种超低功耗异步电路设计方法，称为多阈值空约定逻辑（MTNCL），也称为睡眠约定逻辑（SCL），它结合了多阈值CMOS（MTCMOS）和空约定逻辑（NCL），产生显着的功耗降低，而没有任何缺点的应用MTCMOS同步电路。与通常导致大面积开销的其他功耗降低技术相比，MTNCL电路实际上比其原始NCL版本更小。MTNCL利用高Vt晶体管来选通低Vt逻辑块的电源和接地，以在空闲时提供快速切换和非常低的泄漏功率。为了证明MTNCL的优势，我们设计了一些32位IEEE单精度浮点协处理器，以供比较，这些协处理器采用1.2 V IBM 8RF-LM 130 nm CMOS工艺：原始NCL、仅组合逻辑（C/L）休眠的MTNCL、位式MTNCL（BWMTNCL）、具有C/L和完成逻辑休眠的MTNCL、具有C/L、完成逻辑和寄存器休眠的MTNCL，MTNCL具有安全睡眠架构和同步MTCMOS。这些设计在吞吐量、面积、动态能量和空闲功率方面进行了比较，显示了各种MTNCL架构之间的权衡，并且最佳MTNCL设计在各个方面都比原始NCL设计要好得多，并且比同步MTCMOS设计要好得多面积、每次操作的能量和空闲功率，尽管同步设计可以运行得更快。
This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL), also known as Sleep Convention Logic (SCL), which combines Multi-Threshold CMOS (MTCMOS) with NULL Convention Logic (NCL), to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L) slept, Bit-Wise MTNCL (BWMTNCL), MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster.