Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking

Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking
复制标题

用于实时对象跟踪的基于 FPGA 的粒子滤波的功耗性能分析

DOI:
10.1007/978-3-319-61566-0_41
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发表时间:
2017
期刊:
Advances in Intelligent Systems and Computing (AISC)
影响因子:
--
通讯作者:
and K. Oguri
and K. Oguri
中科院分区:
--
文献类型:
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作者:
A. Tahara;Y. Hayashida;T. T. Thu;Y. Shibata;and K. Oguri

文献摘要

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具有紧凑的基于现场可编程门阵列的结构的实时图像处理在动态状态空间模型中起着关键作用。提出了一种基于流处理结构和并行重采样算法的高能效粒子滤波的FPGA加速结构。粒子滤波通过预测、似然计算和重采样三个步骤来解决状态估计问题。该方法通过在输入图像帧的有效像素区进行重采样,同时在同步区执行预测,实现了目标的实时跟踪。重点介绍了采用不同时钟频率和不同资源利用率的FPGA实现方案。结果表明,与较大的电路尺寸和时钟频率(27 MHz)相比,具有加速时钟频率(135 MHz)的紧凑型结构的功耗有所不同。有趣的是,时钟频率较低的较大架构显示出较低的功耗。
Real-time image processing with a compact FPGA-based architecture plays a key role in dynamic state-space models. This paper presents an energy efficient FPGA acceleration architecture of a particle filter, which is based on stream processing structure with a parallel resampling algorithm. Particle filters solve the state estimation problems with three steps: prediction, likelihood calculation and resampling. By accomplishing the resampling in a valid pixel area of an input image frame, while executing prediction in a synchronization region, our approach achieves real-time object tracking. This paper mainly highlights implementation alternatives using different clock frequencies and resource usages of FPGA. The result shows the comparisons of power consumption for the compact architecture with an accelerated clock frequency (135 MHz) compared to the larger circuit size with clock frequency (27 MHz). Interestingly, the larger architecture with a slower clock frequency shows lower power consumption.