Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures
Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures
复制标题
表征和缓解空间自动机处理架构中的输出报告瓶颈
DOI：
10.1109/hpca.2018.00069
复制
发表时间：
2018
期刊：
影响因子：
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通讯作者：
K. Skadron
中科院分区：
文献类型：
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作者：
J. Wadden;K. Angstadt;K. Skadron
自动机处理的重要性已经复兴，因为它对“大数据”的模式匹配和模式挖掘的有用性。尽管由于无法预测的内存访问，瓶颈von Neumann处理器已知大规模自动机处理，但空间体系结构在自动机处理下出色。空间体系结构可以通过将自动机态在可重构数组中接线，从而实现自动机图，从而允许并行自动机态计算和点对点状态过渡。但是，由于状态的物理位置，输出处理架构设计，I/O资源以及架构的大量并行性质，空间自动机处理体系结构可能会遭受输出限制（商业系统中的255倍！）。为了了解这种瓶颈，我们对一组逼真的自动机处理基准的输出要求进行了第一个已知的表征。我们发现大多数基准测试都经常报告，但是很少有任何一次报告任何一次。这种观察激发了新的输出压缩方案和报告体系结构。我们评估了一种纯粹的软件自动机转换的好处，并表明可以大大降低输出报告成本（在没有硬件修改的情况下最多提高了40％的性能。然后，我们在商业空间空间自动机处理器的报告体系结构中探索瓶颈，并提出一个新的架构可提高性能高达5.1倍。
Automata processing has seen a resurgence in importance due to its usefulness for pattern matching and pattern mining of "big data." While large-scale automata processing is known to bottleneck von Neumann processors due to unpredictable memory accesses, spatial architectures excel at automata processing. Spatial architectures can implement automata graphs by wiring together automata states in reconfigurable arrays, allowing parallel automata state computation, and point-to-point state transitions on-chip. However, spatial automata processing architectures can suffer from output constraints (up to 255x in commercial systems!) due to the physical placement of states, output processing architecture design, I/O resources, and the massively parallel nature of the architecture. To understand this bottleneck, we conduct the first known characterization of output requirements of a realistic set of automata processing benchmarks. We find that most benchmarks report fairly frequently, but that few states report at any one time. This observation motivates new output compression schemes and reporting architectures. We evaluate the benefit of one purely software automata transformation and show that output reporting costs can be greatly reduced (improving performance by up to 40% without hardware modification. We then explore bottlenecks in the reporting architecture of a commercial spatial automata processor and propose a new architecture that improves performance by up to 5.1x.