A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter
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DOI：
10.1109/jssc.2015.2403373
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发表时间：
2015-05-01
影响因子：
5.4
通讯作者：
Craninckx, Jan
中科院分区：
文献类型：
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作者：
Raczkowski, Kuba;Markulic, Nereo;Craninckx, Jan
本文介绍了一种28 nm CMOS小数分频采样锁相环。由于使用了一个以采样时钟为工作时钟的10位、0.55 ps/LSB数字-时间转换器（DTC）电路，因此可以实现分数相位锁定，而相位噪声性能几乎没有损失。被认为是一个实际的DTC实现的性能限制，并提出了减少这些限制的技术。例如，后台校准可保证适当的DTC增益，从而减少杂散。在10 GHz工作频率下，当存在-43 dBc的最差情况分数杂散时，系统可实现-38 dBc的积分相位噪声（280 fs RMS抖动）。带内相位噪声为-104 dBc/Hz。B类VCO的调谐范围为9.2 GHz至12.7 GHz（32%）。频率合成器（包括VCO）的总功耗为13 mW（采用0.9 V和1.8 V电源）。
This paper describes a fractional-N subsampling PLL in 28 nm CMOS. Fractional phase lock is made possible with almost no penalty in phase noise performance thanks to the use of a 10 bit, 0.55 ps/LSB digital-to-time converter (DTC) circuit operating on the sampling clock. The performance limitations of a practical DTC implementation are considered, and techniques for minimizing these limitations are presented. For example, background calibration guarantees appropriate DTC gain, reducing spurs. Operating at 10 GHz the system achieves -38 dBc of integrated phase noise (280 fs RMS jitter) when a worst case fractional spur of -43 dBc is present. In-band phase noise is at the level of -104 dBc/Hz. The class-B VCO can be tuned from 9.2 GHz to 12.7 GHz (32%). The total power consumption of the synthesizer, including the VCO, is 13 mW from 0.9 V and 1.8 V supplies.