Monolithic DC-DC converter analysis and MOSFET gate voltage optimization
Monolithic DC-DC converter analysis and MOSFET gate voltage optimization
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单片 DC-DC 转换器分析和 MOSFET 栅极电压优化
DOI：
10.1109/isqed.2003.1194746
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
E. Friedman
中科院分区：
文献类型：
--
作者：
V. Kursun;S. Narendra;V. De;E. Friedman
本文介绍了一种高效的单片降压变换器的设计。提出了一种低摆幅MOSFET栅极驱动技术，提高了DC-DC变换器的效率特性。建立了降压变换器的寄生阻抗模型。利用该模型，描述了基于0.18 /spl mu/m CMOS技术将降压转换器的有源和无源器件集成到同一芯片上的设计空间。功率MOSFET效率最大化的最佳栅极电压摆幅低于标准的全电压摆幅。采用低摆幅DC-DC转换器实现1.8伏到0.9伏的电压转换，在102 MHz的开关频率下，效率达到88%。与全摆幅DC-DC变换器相比，低摆幅DC-DC变换器的功耗降低24.5%，效率提高3.9%。
The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 /spl mu/m CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.