BTI reliability of 45 nm high-K + metal-gate process technology
BTI reliability of 45 nm high-K + metal-gate process technology
复制标题
DOI：
10.1109/relphy.2008.4558911
复制
发表时间：
2008-07
期刊：
影响因子：
--
通讯作者：
S. Pae;M. Agostinelli;M. Brazier;R. Chau;G. Dewey;T. Ghani;M. Hattendorf;J. Hicks;J. Kavalieros;K. Kuhn;M. Kuhn;J. Maiz;M. Metz;K. Mistry;C. Prasad;S. Ramey;A. Roskowski;J. Sandford;C. Thomas;J. Thomas;C. Wiegand;J. Wiedemer
中科院分区：
文献类型：
--
作者：
S. Pae;M. Agostinelli;M. Brazier;R. Chau;G. Dewey;T. Ghani;M. Hattendorf;J. Hicks;J. Kavalieros;K. Kuhn;M. Kuhn;J. Maiz;M. Metz;K. Mistry;C. Prasad;S. Ramey;A. Roskowski;J. Sandford;C. Thomas;J. Thomas;C. Wiegand;J. Wiedemer
本文对45nm高k +金属栅极（HK+MG）晶体管的偏置温度不稳定性（BTI）进行了表征，并对其降解机理进行了讨论。未优化HK薄膜堆栈的晶体管在早期开发阶段表现出预先存在的陷阱和大量的迟滞，这与文献一致。优化后的HK工艺表明，NMOS和PMOS在HK+MG晶体管上的BTI性能在匹配电场下优于SiON，在目标应用领域可达到30%以上。最后的过程也显示出由于快速陷阱而没有迟滞，从而使我们能够表征其内在的退化机制。在优化的工艺中，NMOS BTI主要归因于HK本体和HK/SiON界面层（IL）区域的电子捕获。另一方面，PMOS的BTI退化主要是由界面驱动的，并且与传统的SiON晶体管非常相似。
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.