Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit
Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit
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DOI：
10.7567/jjap.55.04ef02
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发表时间：
2016-03
影响因子：
1.5
通讯作者：
X. Zhang;F. An;Lei Chen;H. Mattausch
中科院分区：
文献类型：
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作者：
X. Zhang;F. An;Lei Chen;H. Mattausch
作为一种替代传统的单指令多数据（SIMD）模式的解决方案与自组织映射（SOM）神经网络模型的大规模并行性，本文报告了一个基于记忆的学习矢量量化（LVQ）的建议，这是SOM的一个变种。一个双模式LVQ系统，使片上学习和分类，实现了使用可重构流水线与并行p字输入（R-PPPI）架构。由于重新使用R-PPPI来解决这两种模式中最严格的计算需求，与以前的LVQ实现相比，功耗和Si面积消耗可以显着降低。此外，所设计的LVQ ASIC在特征向量维度和参考向量数量方面具有很高的灵活性，允许执行许多不同的机器学习应用。制造的测试芯片在180 nm CMOS并行8字输入和102 K位片上存储器实现了66.38 mW的低功耗（在75 MHz和1.8 V）和高学习速度的时钟周期每个d维样本向量，其中R是参考向量数。
As an alternative to conventional single-instruction-multiple-data (SIMD) mode solutions with massive parallelism for self-organizing-map (SOM) neural network models, this paper reports a memory-based proposal for the learning vector quantization (LVQ), which is a variant of SOM. A dual-mode LVQ system, enabling both on-chip learning and classification, is implemented by using a reconfigurable pipeline with parallel p-word input (R-PPPI) architecture. As a consequence of the reuse of R-PPPI for solving the most severe computational demands in both modes, power dissipation and Si-area consumption can be dramatically reduced in comparison to previous LVQ implementations. In addition, the designed LVQ ASIC has high flexibility with respect to feature-vector dimensionality and reference-vector number, allowing the execution of many different machine-learning applications. The fabricated test chip in 180 nm CMOS with parallel 8-word inputs and 102 K-bit on-chip memory achieves low power consumption of 66.38 mW (at 75 MHz and 1.8 V) and high learning speed of clock cycles per d-dimensional sample vector where R is the reference-vector number.