Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies
Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies
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DOI：
10.1109/tns.2007.910125
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发表时间：
2007-12
影响因子：
1.8
通讯作者：
B. Narasimham;B. Bhuva;peixiong zhao;L. Massengill;M. Gadlage;O. Amusan;W. T. Holman;A. Witulski;W. H. Robinson;J. Black;J. Benedetto;P. Eaton
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文献类型：
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作者：
B. Narasimham;B. Bhuva;peixiong zhao;L. Massengill;M. Gadlage;O. Amusan;W. T. Holman;A. Witulski;W. H. Robinson;J. Black;J. Benedetto;P. Eaton
利用自主脉冲特性测量技术，对130 nm和90 nm CMOS工艺中重离子产生的SET脉冲宽度分布进行了实验测量。在130 nm工艺中，对于400 ps至700 ps之间的SET脉冲，事件截面最高，而在90 nm工艺中，在500 ps至900 ps的范围内的SET脉冲占主导地位。随着比例的增加，更长的SET脉冲的概率增加，这是决定先进技术中组合逻辑软错误的关键因素。混合模式3D-TCAD模拟表明，脉冲宽度的变化是由罢工位置的变化。
The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.