BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
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DOI：
10.1109/rtas48715.2020.00011
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发表时间：
2020-04
期刊：
影响因子：
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通讯作者：
F. Farshchi;Qijing Huang;H. Yun
中科院分区：
文献类型：
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作者：
F. Farshchi;Qijing Huang;H. Yun
多核处理器的时间可预测性差是一个众所周知的问题，它由于共享内存资源的竞争而阻碍了它们在实时系统中的应用。在本文中，我们提出了带宽调节单元(BRU)，这是一个插入式硬件模块，能够以细粒度的时间间隔对每核的内存带宽进行调节。此外，BRU还能够集体调整多个内核的内存访问带宽，以提高带宽利用率。除了消除软件调整方法的开销外，我们使用SD-VBS和合成基准测试的评估结果表明，BRU提高了实时任务的时间可预测性，同时它让尽力而为的任务更好地利用内存系统带宽。此外，我们还综合了一个7 nm工艺节点的设计，结果表明BRU的芯片面积开销可以忽略不计。
Poor time-predictability of the multicore processors is a well-known issue that hinders their adoption in the real-time systems due to contention in the shared memory resources. In this paper, we present the Bandwidth Regulation Unit (BRU), a drop-in hardware module that enables per-core memory bandwidth regulation at fine-grained time intervals. Additionally, BRU has the ability to regulate the memory access bandwidth of multiple cores collectively to improve bandwidth utilization. Besides eliminating the overhead of software regulation methods, our evaluation results using SD-VBS and synthetic benchmarks show that BRU improves time-predictability of real-time tasks, while it lets the best-effort tasks to better utilize the memory system bandwidth. In addition, we have synthesized our design for a 7nm technology node and show that the chip area overhead of BRU is negligible.