Design technique for interpolated flash ADC
Design technique for interpolated flash ADC
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内插式闪存ADC设计技术
DOI：
10.1109/icsict.2010.5667805
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
B. Zhao
中科院分区：
文献类型：
--
作者：
H. Tang;H. Zhao;S. Fan;X. Wang;L. Lin;Q. Fang;J. Liu;A. Wang;B. Zhao
模数转换在各种电子系统中发挥着重要作用，包括信号处理、通信和存储。特别是内插式闪存ADC已广泛应用于需要非常高采样速度的高速系统中。显然，实际的ADC设计非常具有挑战性，这主要取决于经验和试错技巧。对于闪存 ADC 设计也是如此，电路设计人员经常对 ADC 芯片性能与其架构、电路、器件和技术细节之间的复杂因素感到困惑。随着系统性能的不断提高和市场需求的迅速加剧，设计人员必须在 ADC 设计中做出快速、合理的决策，以平衡各种设计因素。本文报告了电容插值闪存 ADC 的全面设计矩阵分析和定量设计方法，旨在解决设计挑战。它定量地描述了ADC速度、插值、级数、前置放大器带宽、晶体管寄生效应、晶体管尺寸和技术参数等关键因素之间的复杂关系。定量设计技术旨在使设计人员能够在闪存ADC设计中做出快速和预测性决策，以在实践中实现权衡和性能优化。介绍了 90/130nm CMOS 的设计示例。
Analog-to-digital conversion plays an essential role in all kinds of electronics systems, including signal processing, communications and storage. In particular, interpolated flash ADC has been widely used in high-speed systems requiring very high sampling speed. Obviously, practical ADC design is very challenging, which has been dominated by experiences and trial-and-error skills. This is true to flash ADC designs too where circuit designers have often been puzzled by complex factors between ADC chip performance and its architecture, circuit, device and technological details. As system performance continues advance and market demands intensify rapidly, it is imperative for designers to make quick and rational decisions in ADC designs to balance various design factors. This paper reports a comprehensive design matrix analysis and quantitative design approach for capacitive interpolated flash ADCs aiming to address the design challenges. It describes quantitatively the complex relationship among critical factors including ADC speed, interpolation, stage number, pre-amplifier bandwidth, transistor parasitic effects, transistor size and technology parameters, etc. The quantitative design technique intends to enable designers to make rapid and predictive decisions in flash ADC designs to achieve both trade-offs and performance optimization in practice. Design examples in 90/130nm CMOS are presented.