A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator
A $148fs_{rms}$ Integrated Noise 4 MHz Bandwidth Second-Order $\Delta\Sigma$ Time-to-Digital Converter With Gated Switched-Ring Oscillator
复制标题
具有门控开关环振荡器的 148fs_{rms}$ 集成噪声 4 MHz 带宽二阶 $DeltaSigma$ 时间数字转换器
DOI：
10.1109/tcsi.2014.2321195
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Seonghwan Cho
中科院分区：
文献类型：
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作者：
Wonsik Yu;KwangSeok Kim;Seonghwan Cho
本文提出了一种采用开关环形振荡器（SRO）和门控开关环形振荡器（GSRO）的二阶Δ T时间数字转换器（TDC）。与传统的多级噪声整形（MASH）TDC使用SRO，所提出的TDC不需要复杂的校准，以补偿振荡器之间的频率差的误差。此外，所提出的TDC的性能进行了分析，包括非理想的，如相位噪声，失配，和PVT的变化。原型1-1 MASH TDC在400 MS/s的4 MHz信号带宽下实现了148 f srms的集成噪声，同时在65 nm CMOS工艺中消耗6.55 mW。
This paper presents a second-order ΔΣ time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performance of the proposed TDC is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations. The prototype 1-1 MASH TDC achieves 148 f srms integrated noise in 4 MHz signal bandwidth at 400 MS/s while consuming 6.55 mW in a 65 nm CMOS process.