Bumpless flip chip packages
Bumpless flip chip packages
复制标题
无凸点倒装芯片封装
DOI：
10.1109/emap.2002.1188833
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
T.K.A. Yang
中科院分区：
文献类型：
--
作者：
C.W.C. Lin;S. Chiang;T.K.A. Yang
目前的倒装芯片封装活动分为两种非常不同的方法。一个是进一步改进凸块结构，特别关注凸块结构、无铅、底部填充材料和板级可靠性问题。另一个是开发无凸点的最终结构，以实现更好的电气特性并满足更严格的环境规范。本文提出了一种新的无凸块倒装芯片封装的成本/性能驱动的设备。使用电化学电镀（ECP）方法，制造低至25 /spl mu/m线/空间的细线迹线的图案，并将其直接连接到管芯焊盘，而不使用引线键合或焊料凸块或内插器基板或诸如薄膜溅射的真空工艺。这种方法能够使用单层金属生产高达256个I/O的区域阵列封装。封装到板级连接是通过一系列树脂填充端子实现的，这些端子在封装和组装板之间提供了出色的机械顺应性。该封装中提供信号重新分布的电镀细线迹线与晶圆级封装中的类似。更重要的是，它们的“扇出”特性是使高引脚数器件能够容纳在这种封装的区域阵列格式中的关键。详细的设计概念和处理技术与此包进行了讨论。各种成本/性能器件的考虑进行了讨论。最后，设计集成的重要性，在技术开发周期的早期与封装级和板级的可靠性突出作为一个关键的路径，以成本驱动和/或性能驱动的设备的最佳设计。
Current flip chip packaging activities are divided into two very different approaches. One is to further improve the bumped structure with particular focus on bump structure, lead-free, under-fill material and board level reliability issues. The other is to develop the ultimate structure without bumps to achieve even better electrical characteristics and meet more stringent environmental specifications. This paper presents a novel bumpless flip chip package for cost/performance driven devices. Using the electrochemical plating (ECP) method, a pattern of fine-line traces down to 25 /spl mu/m line/space is fabricated and connected to the die pads directly without using wire-bonds or solder bumps or an interposer substrate or vacuum processes such as thin film sputtering. This method enables the production of area array packages up to 256 I/O using a single layer of metal. Package-to-board level connection is made through a series of resin-filled terminals which provide excellent mechanical compliancy between the package and the assembled board. The electroplated fine-line traces which provide signal re-distribution in this package are similar to those in wafer level packages. More importantly, their "fan-out" feature is the key to enabling high lead count devices to be accommodated in the area array format with this package. Details of the design concepts and processing technology associated with this package are discussed. Considerations for various cost/performance devices are discussed. Finally, the importance of design integration early in the technology development cycle with package-level and board-level reliability is highlighted as a critical path to an optimal design for cost-driven and/or performance-driven devices.