On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
复制标题
针对安全关键应用的基于 SRAM 的 FPGA 的可调谐容错电路设计
DOI：
10.1145/1403375.1403456
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
H. Guzmán
中科院分区：
文献类型：
--
作者：
L. Sterpone;M. Aguirre;J. Tombs;H. Guzmán
关键任务应用，如空间或航空电子设备，越来越多地要求其电子系统具有高容错能力。在容错特性中，电子系统的性能和成本仍然是空间和航空电子市场的主要因素。特别是在考虑基于sram的fpga时，为了保证期望的容错程度，通常需要采用基于三模冗余的特定强化技术。在有效地提高容错能力的同时，这些技术带来了严重的性能下降和巨大的面积开销，从而导致更高的设计成本。在本文中，我们提出了一种创新的设计流程，允许在基于sram的FPGA器件中实现具有不同容错能力程度的容错电路。我们引入了一个新的度量，允许设计人员精确地估计和设置所需的容错能力。在一个实际的工业案例研究中进行的实验分析证明了我们的方法的有效性。
Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular Redundancy need to be adopted in order to guarantee the desired fault tolerance degree. While effectively increasing the fault tolerance capability, these techniques introduce an important performance degradation and a dramatic area overhead, that results in higher design costs. In this paper, we propose an innovative design flow that allow the implementation of fault tolerance circuits in SRAM-based FPGA devices with different fault tolerance capability degrees. We introduce a new metric that allows a designer to precisely estimate and set the desired fault tolerance capabilities. Experimental analysis performed on a realistic industrial-type case study demonstrates the efficiency of our methodology.