Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications
Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications
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适用于内存计算应用的紧凑型铁电可编程多数门
DOI：
10.1109/iedm45625.2022.10019400
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发表时间：
2022
期刊：
影响因子：
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通讯作者：
Amrouch, Hussam
中科院分区：
文献类型：
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作者：
Deng, Shan;Benkhelifa, Mahdi;Thomann, Simon;Faris, Zubair;Zhao, Zijian;Huang, Tzu-Jung;Xu, Yixin;Narayanan, Vijaykrishnan;Ni, Kai;Amrouch, Hussam
提出了一种结构紧凑、新颖的铁电可编程多数门，并研究了其在二进制神经网络中的应用。我们证明：i）通过在晶体管的栅极上集成N个金属-铁电-金属（MFM）电容器，（1 T-N-MFM结构），实现了一种非易失性可编程多数门，实现了门输入和极化之间的逻辑与运算，并通过理论和实验验证了所设计的三输入MAJ逻辑与门的功能; iii）XNOR门的3输入MAJ的紧凑实现，其仅利用并联连接的AND门的3输入MAJ中的五个; iv）XNOR门的MAJ的应用以替代BNN中的XNOR门和加法器树的第一层，以在消除能量的基础上节省高达21倍的面积。由于内存中计算的性质，需要大量的内存访问。
In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.