A high-speed and low-power up/down counter in 0.18-μm CMOS technology
A high-speed and low-power up/down counter in 0.18-μm CMOS technology
复制标题
采用 0.18μm CMOS 技术的高速、低功耗加/减计数器
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Qingsheng Hu
中科院分区：
文献类型：
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作者：
Tang Zhang;Qingsheng Hu
本文提出了一种高速、节能的可逆计数器。计数器采用简单的电路架构，因此可以节省面积和功耗。此外，还采用了多种时序优化方法，包括逻辑工作、关键组件的全定制方法以及精心的手动布局和布线，以最大限度地减少延迟并提高工作频率。该计数器采用TSMC 0.18μm CMOS工艺制作，测量结果表明其时钟频率可达1.6GHz，在1.8V供电下功耗为7.7mW。
A high speed and power efficient up/down counter is proposed in this paper. Straightforward circuit architecture is adopted for the counter, thus the area and power penalty can be saved. Additionally, several timing optimal methods including logic effort, full-custom methodology for key components and elaborate manual placement and routing are employed to minimize the delay and improve the working frequency. This counter has been fabricated in TSMC 0.18μm CMOS process and the measurement results show that its clock frequency can be up to 1.6GHz and the power dissipation is 7.7mW under 1.8V power supply.