A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs
A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs
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DOI：
10.1109/jssc.2011.2144010
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发表时间：
2011-05
影响因子：
5.4
通讯作者：
Seung-hyun Lim;Jimin Cheon;Youngcheol Chae;Wun-ki Jung;Dong-Hun Lee;Minho Kwon;Kwi-sung Yoo;S. Ham
中科院分区：
文献类型：
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作者：
Seung-hyun Lim;Jimin Cheon;Youngcheol Chae;Wun-ki Jung;Dong-Hun Lee;Minho Kwon;Kwi-sung Yoo;S. Ham
本文提出了一种低功耗240帧/秒2.1 M像素CMOS图像传感器与列共享循环（CY）ADC。采用两列共享的CY-ADC结构和两级堆叠式ADC布局，实现低功耗和小像素间距设计。所提出的CY-ADC仅使用一个OTA和四个电容。提出了使用级联中继器的分布式时钟方案，以降低所需的峰值电流。原型传感器采用0.13 μ m1 P4 M工艺制造，像素间距为2.25 μm。设计的10位ADC在1.5 V电源电压下，每通道功耗仅为90 μW。实测DNL和INL分别为+0.59/-0.83 LSB和+2.8/-3.6 LSB。测得的最大像素速率为500 Mpixels/s，总功耗为300 mW。
This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- μm 1P4M process with pixel pitch of 2.25 μm . The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are +0.59/-0.83 LSB and +2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.