Probabilistic error detection and correction in switched capacitor circuits using checksum codes
Probabilistic error detection and correction in switched capacitor circuits using checksum codes
复制标题
使用校验和代码进行开关电容器电路中的概率错误检测和校正
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
A. Chatterjee
中科院分区：
文献类型：
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作者：
Md Imran Momtaz;Suvadeep Banerjee;A. Chatterjee
过去，已经开发出使用校验和代码在线性数字和模拟电路中进行错误检测的技术，并被证明是非常高效的。虽然错误检测是一个已解决的问题，但由于诊断故障系统状态并实时纠正它们所涉及的时间和面积开销，纠错已被证明是困难的。为了解决校正问题，人们提出了数字电路的实时概率校正机制，以概率的方式校正状态错误，从而绕过了准确的错误诊断过程。由于所涉及的误差反馈机制的性质，这种技术很难在不改变模拟传递函数的情况下应用于连续时间模拟电路。然而，开关电容器电路具有固有的优势；它们复制了模拟连续时间行为，同时保留了数字时钟的优点。在这项工作中，我们展示了如何使用概率校正算法，通过利用数字时钟在电路的无错误和受错误影响的时钟周期之间提供的时间间隔来检测和纠正开关电容器电路中的错误。通过在未来时钟周期开始之前实时概率地纠正错误，利用数字时钟提供的优势在开关电容器滤波器中提供高保真模拟性能，从而以低成本实现显着的 SNR 优势。
In the past, techniques for error detection in linear digital and analog circuits using checksum codes have been developed and shown to be highly efficient. While error detection is a solved problem, error correction has proved to be difficult due to the time and area overheads involved in diagnosing failed system states and correcting them in real-time. To solve the correction problem, real-time probabilistic correction mechanisms have been proposed for digital circuits that correct for state errors in a probabilistic manner, circumventing the process of accurate error diagnosis. Such a technique is difficult to apply to continuous-time analog circuits without altering the analog transfer function, due to the nature of error feedback mechanisms involved. However, switched-capacitor circuits offer intrinsic advantages; they replicate analog continuous-time behavior while retaining the benefits of a digital clock. In this work, we show how errors in switched-capacitor circuits can be detected and corrected, using probabilistic correction algorithms, by taking advantage of the separation in time afforded by the use of a digital clock between error-free and error-affected clock cycles of the circuit. By probabilistically correcting errors in real-time before the onset of future clock cycles, the advantages offered by digital clocks are exploited to deliver high-fidelity analog performance in switched-capacitor filters resulting in significant SNR benefits at low cost.