Logic Synthesis for Digital In-Memory Computing
Logic Synthesis for Digital In-Memory Computing
复制标题
数字内存计算的逻辑综合
DOI：
10.1145/3508352.3549348
复制
发表时间：
2022
期刊：
影响因子：
--
通讯作者：
Ewetz, Rickard
中科院分区：
文献类型：
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作者：
Rashed, Muhammad Rashedul;Jha, Sumit Kumar;Ewetz, Rickard
在内存中处理是一种很有前途的解决方案策略，用于加速数据密集型应用程序。虽然模拟内存计算非常高效，但有限的精度仅适用于近似计算应用。数字内存计算提供了加速高保证应用所需的确定性精度。现有技术的数字存储器内计算方案依赖于将算术运算手动分解成存储器内计算内核。相比之下，传统的数字电路是使用复杂和自动化的设计流程来合成的。在本文中，我们提出了一个逻辑综合框架，称为逻辑映射到数字存储器中的计算内核，可以使用非易失性存储器的高级应用程序。首先，我们提出的技术分解元素的算术运算到内存内核，同时最大限度地减少内存操作的数量。接下来，优化存储器内操作的顺序以最小化非易失性存储器利用率。最后，数据布局重组被用来有效地加速稀疏矩阵向量乘法运算占主导地位的应用程序。实验结果表明，所提出的综合方法提高了77%和20%的最先进的定点乘法的面积和延迟，分别。在Suite Sparse Matrix Collection的科学计算应用程序上，所提出的设计分别将面积、延迟和能量提高了3.6倍、2.6倍和8.3倍。
Processing in-memory is a promising solution strategy for accelerating data-intensive applications. While analog in-memory computing is extremely efficient, the limited precision is only acceptable for approximate computing applications. Digital in-memory computing provides the deterministic precision required to accelerate high assurance applications. State-of-the-art digital in-memory computing schemes rely on manually decomposing arithmetic operations into in-memory compute kernels. In contrast, traditional digital circuits are synthesized using complex and automated design flows. In this paper, we propose a logic synthesis framework called LOGIC for mapping high-level applications into digital in-memory compute kernels that can be executed using non-volatile memory. We first propose techniques to decompose element-wise arithmetic operations into in-memory kernels while minimizing the number of in-memory operations. Next, the sequence of the in-memory operation is optimized to minimize non-volatile memory utilization. Lastly, data layout re-organization is used to efficiently accelerate applications dominated by sparse matrix-vector multiplication operations. The experimental evaluations show that the proposed synthesis approach improves the area and latency of fixed-point multiplication by 77% and 20% over the state-of-the-art, respectively. On scientific computing applications from Suite Sparse Matrix Collection, the proposed design improves the area, latency and, energy by 3.6X, 2.6X, and 8.3X, respectively.