An efficient test data reduction technique through dynamic pattern mixing across multiple fault models
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models
复制标题
通过跨多个故障模型的动态模式混合有效的测试数据缩减技术
DOI：
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发表时间：
2011
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通讯作者：
V. Agrawal
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作者：
Srinivasulu Alampally;R. Venkatesh;Priyadharshini Shanmugasundaram;R. Parekhji;V. Agrawal
ATPG工具生成的模式是大型SOC测试数据的主要组成部分。随着芯片尺寸的增加、涉及IP核的更高集成度以及在新技术中需要针对多个故障模型的模式以更好地覆盖缺陷，足够的覆盖率以及合理的测试数据量和应用时间的问题主导了测试的经济性。我们解决的问题，产生紧凑的测试模式集跨多个故障模型。传统方法对每个故障模型使用单独的ATPG，并且在通过静态或动态压缩的模式生成期间，或者在模式生成之后通过针对静态压缩在所有故障模型上模拟所有模式来最小化模式。我们提出了一种新的ATPG技术，所有感兴趣的故障模型同时在一个单一的ATPG运行为目标。图案以小间隔生成，每个间隔由16、32或64个图案组成。在每个间隔中，故障模型特定的ATPG设置为它们各自的故障模型生成单独的模式集。然后，有效性标准恰好选择这些模式集之一。所选的集涵盖了需要最多其他模式的非目标故障。重复模式生成间隔，直到实现对所有感兴趣的模型的故障的所需覆盖。所有选定间隔模式集的总和为DUT的总体测试集。在工业电路上的实验表明，模式数减少了21%至68%。该技术独立于任何特殊的ATPG工具或扫描压缩技术，并且不需要在现有的ATPG系统中进行更改或提供额外的支持。
ATPG tool generated patterns are a major component of test data for large SOCs. With increasing sizes of chips, higher integration involving IP cores and the need for patterns targeting multiple fault models for better defect coverage in newer technologies, the issues of adequate coverage and reasonable test data volume and application time dominate the economics of test. We address the problem of generating compact set of test patterns across multiple fault models. Traditional approaches use separate ATPG for each fault models and minimize patterns either during pattern generation through static or dynamic compaction, or after pattern generation by simulating all patterns over all fault models for static compaction. We propose a novel ATPG technique where all fault models of interest are concurrently targeted in a single ATPG run. Patterns are generated in small intervals, each consisting of 16, 32 or 64 patterns. In each interval fault model specific ATPG setups generate separate pattern sets for their respective fault model. An effectiveness criterion then selects exactly one of those pattern sets. The selected set covers untargeted faults that would have required the most additional patterns. Pattern generation intervals are repeated until required coverage for faults of all models of interest is achieved. The sum total of all selected interval pattern sets is the overall test set for the DUT. Experiments on industrial circuits show pattern count reductions of 21% to 68%. The technique is independent of any special ATPG tool or scan compression technique and requires no change or additional support in an existing ATPG system.