An Improved Fault Simulation Approach Based on Verilog with Application to ISCAS Benchmark Circuits
An Improved Fault Simulation Approach Based on Verilog with Application to ISCAS Benchmark Circuits
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基于Verilog的改进故障仿真方法及其在ISCAS基准电路中的应用
DOI：
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发表时间：
2006
期刊：
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通讯作者：
W. Jone
中科院分区：
文献类型：
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作者：
S.R. Das;S. Mukherjee;H.M. Petrm;M. Assaf;M. Sahinoglu;W. Jone
本文提出了一种基于硬件描述语言（HDL）门级网表规范的ISCAS 85组合基准电路的故障模拟方法。该方法充分利用Verilog语言中现有的强制和释放功能，通过合理利用Verilog语法并将其应用于故障建模，构建了一个有效的故障模拟器。所实现的仿真器系统能够仿真所有的ISCAS 85组合电路。实验结果表明，访问HDL模拟器的源代码或其修改是不需要计算故障响应从被测电路（CUT）。建议的模拟器是平台独立的，从而使其效用大大值得
This paper presents an approach to fault simulation in the particular context of ISCAS 85 combinational benchmark circuits based on hardware description language (HDL) specification of their gate level netlists. The approach, exploiting the existing force and release features available in Verilog, builds an effective fault simulator by properly utilizing Verilog syntax with application to fault modeling. The implemented simulator system is able to emulate all of the ISCAS 85 combinational circuits. Experimental results show that access to the source code of HDL simulator or its modification is not a requirement to compute faulty responses from a circuit under test (CUT). The proposed simulator is platform independent, thereby making its utility substantially worthwhile