Realization of a silicon nanowire vertical surround-gate field-effect transistor
Realization of a silicon nanowire vertical surround-gate field-effect transistor
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DOI：
10.1002/smll.200500181
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发表时间：
2006-01-01
期刊：
影响因子：
13.3
通讯作者：
Gösele, U
中科院分区：
文献类型：
--
作者：
Schmidt, V;Riel, H;Gösele, U
半导体纳米线最近引起了相当大的关注。凭借其独特的电学和光学特性，它们为基础研究[1]和技术提供了有趣的前景。各种技术应用，如纳米线作为传感器的一部分，[2]和电子[3，4]和光子设备[5]已经被证明。特别是，电子应用越来越受到关注，因为微电子正在进行的小型化需要新的创新解决方案。半导体纳米线，特别是外延生长的硅(Si)纳米线，由于其与现有工艺的潜在兼容性，被认为是后CMOS(互补金属氧化物半导体)逻辑元件的潜在候选者。与自上而下制造的器件相比，气-液-固(VLS)生长的纳米线的一个主要优势是它们具有明确的表面。这减少了表面散射，这是一个对纳米级设备变得重要的问题。此外，外延生长的纳米线避免了在传统的拾取和放置方法中出现的处理和定位纳米尺寸物体的问题，在这种方法中，设备是通过操纵水平放置的VLS生长的纳米线来制造的。[6]实现纳米线逻辑元件的技术实现的第一步是纳米线晶体管的设计和制造。垂直纳米线的外延生长提供了比其他方法更好的优势：例如，晶体管栅极可以缠绕在垂直取向的纳米线周围。这种缠绕栅极允许更好地对导电通道进行静电栅极控制，并提供了在每个器件面积上驱动比传统平面架构中可能的更多电流的潜力。[7]在本通信中，描述了一种基于外延生长的纳米线制造垂直环绕栅场效应晶体管(VS-FET)的通用工艺。例如，我们使用了硅纳米线，并首次进行了电学表征，证明了所开发的工艺的可行性和该器件的基本功能。图1a显示了传统p型MOSFET的横截面示意图。在这种器件中，通过施加负栅电压，可以在栅极附近产生反转沟道。这形成了导电沟道，该沟道在源极和漏极触点之间电连接p掺杂区域。使用这一概念，硅纳米线VS-FET理想地需要在栅极区域n掺杂而在其他地方p掺杂的纳米线。不幸的是，如果纳米线是以金为催化剂的气-液-固机制[8]生长的，这种具有突变的PNP结构似乎很难实现。这里的困难在于，溶解在催化剂液滴中的掺杂原子可能起到蓄水池的作用，从而在切换到另一种掺杂时产生梯度转变。因此，我们使用了一种由生长在p型衬底上的n掺杂硅纳米线组成的结构(见图1b)。如果栅漏极和栅源极距离不是太长，仍然可以静电地沿着整个导线的长度创建反转沟道。在所提出的配置中，源接触处的p-n结(图1a)被纳米线尖端的Au/n-Si肖特基接触所取代。
Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research [1] as well as for technology. A variety of technical applications, such as nanowires as parts of sensors,[2] and electronic [3, 4] and photonic devices [5] have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid–solid-(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires.[6] The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture.[7] In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a pnp structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism [8] using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant.Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip.