Dual-side and three-dimensional microelectrode arrays fabricated from ultra-thin silicon substrates
Dual-side and three-dimensional microelectrode arrays fabricated from ultra-thin silicon substrates
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DOI：
10.1088/0960-1317/19/7/075008
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发表时间：
2009-07-01
影响因子：
2.3
通讯作者：
Masmanidis, Sotiris C.
中科院分区：
文献类型：
--
作者：
Du, Jiangang;Roukes, Michael L.;Masmanidis, Sotiris C.
一种用于制造平面可植入微电极阵列的方法被证明使用依赖于超薄硅衬底的工艺，该超薄硅衬底的厚度范围从25 μ m到50 μ m。处理这些易碎材料的挑战是通过一个临时的基板支持机制。为了补偿细胞外神经元场的假定电屏蔽，在硅装置的每一侧上限定可单独寻址的电极阵列。深反应离子蚀刻，以创建尖锐的植入式轴的长度可达5毫米。该设备被倒装芯片键合到印刷电路板（PCB）上的各向异性导电胶膜的装置。这种可扩展的组装技术通过形成多个硅和PCB层的堆叠实现了三维（3D）集成。微电极噪声的模拟和测量似乎表明，需要通过电沉积金或其他材料形成的低阻抗表面来确保最佳的信噪比以及低水平的通道间串扰。
A method for fabricating planar implantable microelectrode arrays was demonstrated using a process that relied on ultra-thin silicon substrates, which ranged in thickness from 25 to 50 mu m. The challenge of handling these fragile materials was met via a temporary substrate support mechanism. In order to compensate for putative electrical shielding of extracellular neuronal fields, separately addressable electrode arrays were defined on each side of the silicon device. Deep reactive ion etching was employed to create sharp implantable shafts with lengths of up to 5 mm. The devices were flip-chip bonded onto printed circuit boards (PCBs) by means of an anisotropic conductive adhesive film. This scalable assembly technique enabled three-dimensional (3D) integration through formation of stacks of multiple silicon and PCB layers. Simulations and measurements of microelectrode noise appear to suggest that low impedance surfaces, which could be formed by electrodeposition of gold or other materials, are required to ensure an optimal signal-to-noise ratio as well a low level of interchannel crosstalk.