Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages
Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages
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DOI：
10.1109/tdmr.2012.2194495
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发表时间：
2012-04
影响因子：
2
通讯作者：
Xi Liu;Qiao Chen;V. Sundaram;M. Simmons-Matthews;K. Wachtler;R. Tummala;S. Sitaraman
中科院分区：
文献类型：
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作者：
Xi Liu;Qiao Chen;V. Sundaram;M. Simmons-Matthews;K. Wachtler;R. Tummala;S. Sitaraman
本文介绍了硅通孔 (TSV) 的热机械可靠性研究。 TSV 用于互连堆叠芯片以实现 3D 封装。由于 TSV 的核心包含高热膨胀系数 (CTE) 铜，周围环绕着低 CTE SiO2 和 Si 材料，因此 TSV 的热机械可靠性值得关注。当堆叠和封装具有此类 TSV 的芯片时，与独立式晶圆相比，额外结构和相关材料的存在可能会带来不同的热机械问题。本文提出了 3D 有限元模型，用于研究独立式晶圆和封装堆叠芯片中 TSV 的热机械应力。翘曲测量已用于验证有限元建模方法。有限元模型的结果表明，封装配置中的 TSV 应力通常低于独立式晶圆配置中的 TSV 应力。此外，可以看出，连接相邻芯片的微凸块经历了高强度的非弹性应变，表明这些位置存在可靠性问题。
A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.