Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
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DOI：
10.1145/1973009.1973026
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发表时间：
2011-05
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影响因子：
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通讯作者：
Levent Aksoy;E. Costa;Paulo F. Flores;J. Monteiro
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文献类型：
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作者：
Levent Aksoy;E. Costa;Paulo F. Flores;J. Monteiro
用于无乘法器实现多个常量乘法 (MCM) 的现有优化算法通常以加法和减法运算次数的最小化为目标。由于功耗与硬件数量直接相关，因此这些算法可以间接实现一些功耗降低。然而，在许多情况下，故障在定义功耗方面起着同样重要的作用。对于算术电路来说尤其如此，特别是对于MCM，因为它具有高逻辑深度和大量的重新收敛路径。本文介绍了在门级搜索 MCM 设计最佳区域的精确算法，其中每个常数乘法都以最小深度实现。实验结果表明，与 MCM 算法相比，所提出的算法使 MCM 设计消耗的功耗显着降低。
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subtraction operations. Since power dissipation is directly related to the amount of hardware, some power reduction is indirectly achieved by these algorithms. However, in many cases, glitching plays an equally important role in defining the power consumption. This is specially true for arithmetic circuits, and in particular to MCM due to high logic depth and large number of re-convergent paths. This paper introduces exact algorithms that search the optimal area of an MCM design at gate-level where each constant multiplication is implemented in its minimum depth. Experimental results show that the proposed algorithms lead to MCM designs consuming significantly less power with respect to those obtained by the MCM algorithms.