Analysis and Design of RF CMOS Attenuators
Analysis and Design of RF CMOS Attenuators
复制标题
DOI：
10.1109/jssc.2008.2004325
复制
发表时间：
2008-10
影响因子：
5.4
通讯作者：
H. Dogan;R. Meyer;A. Niknejad
中科院分区：
文献类型：
--
作者：
H. Dogan;R. Meyer;A. Niknejad
对衰减器进行了最小插入损耗（IL）、最大衰减和源负载匹配性能分析。这些结果用于在设计具有宽动态范围的CMOS衰减器时进行权衡，并在0.13 μ m CMOS工艺中设计和制造。该设计采用了两个不相同的级联t级，连续激活以提高线性度。该设计工作在DC-2.5 GHz频段，整个频率范围内的插入损耗为0.9-3.5 dB，最大衰减为42 dB。最坏的情况下S11是- 8.2 dB在整个频带。该设计在中等衰减时实现了+ 20 dBm的IIP3。
Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5 GHz with 0.9-3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is - 8.2 dB across the frequency band. The design achieves an IIP3 of + 20 dBm at mid-attenuation.