Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection
复制标题
具有统一错误检测功能的抗故障攻击加密硬件
DOI：
10.1007/11889700_17
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
A. Taubin
中科院分区：
文献类型：
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作者：
Konrad J. Kulikowski;M. Karpovsky;A. Taubin
传统的基于线性码的硬件错误检测方法对典型或预期的错误和故障进行假设，并将检测能力集中于预期的错误和故障。这些传统方法对于保护加密硬件的硬件实现免受故障攻击来说并不是最佳的。执行基于故障的攻击的对手可能是不可预测的，并且会利用传统实现中的弱点。为了检测这些不需要对预期错误或故障分布进行假设的攻击，我们提出并激发了一种基于鲁棒非线性系统（n，k）错误检测代码的架构。这些代码可以独立于错误分布提供统一的错误检测覆盖范围。它们不会假设攻击者会注入哪些故障或错误，并且与具有相同 (n,k) 的线性代码相比，无法检测到的错误更少。我们还提出了优化方法，可以在鲁棒性级别和硬件实现所需的开销之间进行权衡。
Traditional hardware error detection methods based on linear codes make assumptions about the typical or expected errors and faults and concentrate the detection power towards the expected errors and faults. These traditional methods are not optimal for the protection of hardware implementations of cryptographic hardware against fault attacks. An adversary performing a fault-based attack can be unpredictable and exploit weaknesses in the traditional implementations. To detect these attacks where no assumptions about expected error or fault distributions should be made we propose and motivate an architecture based on robust nonlinear systematic (n,k)-error-detecting codes. These code can provide uniform error detecting coverage independently of the error distributions. They make no assumptions about what faults or errors will be injected by an attacker and have fewer undetectable errors than linear codes with the same (n,k). We also present optimization approaches which provide for a tradeoff between the levels of robustness and required overhead for hardware implementations.