Aging-resilient SRAM design: an end-to-end framework
Aging-resilient SRAM design: an end-to-end framework
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DOI：
10.1109/vts48691.2020.9107571
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发表时间：
2020-04
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影响因子：
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通讯作者：
X. Zuo;S. Gupta
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文献类型：
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作者：
X. Zuo;S. Gupta
晶体管的性能会因老化而降低。偏置温度不稳定性 (BTI) 是纳米级 CMOS 技术中最突出的老化机制。老化退化会导致寿命故障并降低发货芯片的质量。我们开发了端到端 SRAM 设计框架，以在给定约束下最大限度地提高老化弹性。具体来说，我们分析了老化对 SRAM 外围电路的影响，包括地址解码器、预充电、写入电路和读出放大器 (SA)。我们通过量化 ECC 的面积和延迟开销并分别估计具有 ECC 的 SRAM 的寿命良率和 DPPM，探索纠错码 (ECC) 对抗老化的效率。我们还计算了使用 ECC 修复老化故障时的软错误恢复能力。在比较了基于电池尺寸和 ECC 的开销、寿命良率和 DPPM 方面的方法之后，我们可以选择这些方法中的一种或组合来确定在给定约束下针对老化的最佳设计。我们将我们的方法集成到现有的 SRAM 编译器 CACTI [1] 中，为设计人员提供端到端功能。
The performance of transistors degrades due to aging. Bias temperature instability (BTI) is the most prominent aging mechanism in nano-scale CMOS technologies. Aging degradation causes lifetime failures and lowers the quality of shipped chips. We have developed an end-to-end SRAM design framework to maximize the aging resilience under the given constraints. Specifically, we analyze the impact of aging in SRAM peripheral circuits, including address decoder, precharge, write circuit and sense amplifiers (SAs). We explore the efficiency of error-correcting codes (ECC) to combat aging by quantifying the area and delay overheads of ECC and estimating the lifetime yield and DPPM of SRAMs with ECC, respectively. We also calculate the soft error resilience when ECC is used to repair aging failures. After comparing approaches based on cell sizing and ECC in terms of overheads, lifetime yield and DPPM, we can choose either one or a combination of these approaches to identify the optimal design against aging under the given constraints. We integrate our methods into an existing SRAM compiler, CACTI [1], to provide the end-to-end capability to designers.