Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
复制标题
使用符号计算机代数和布尔可满足性对模乘法器进行形式化验证
DOI:
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发表时间:
2022
期刊:
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通讯作者:
R. Drechsler
中科院分区:
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作者:
Alireza Mahzoon;Daniel Große;Christoph Scholl;Alexander Konrad;R. Drechsler
Modular multipliers are the essential components in cryptography and Residue Number System (RNS) designs. Especially, 2n - 1 and 2n + 1 modular multipliers have gained more attention due to their regular structures and a wide variety of applications. However, there is no automated formal verification method to prove the correctness of these multipliers. As a result, bugs might remain undetected after the design phase. In this paper, we present our modular verifier that combines Symbolic Computer Algebra (SCA) and Boolean Satisfiability (SAT) to prove the correctness of 2n - 1 and 2n + 1 modular multipliers. Our verifier takes advantage of three techniques, i.e. coefficient correction, SAT-based local vanishing removal, and SAT-based output condition check to overcome the challenges of SCA-based verification. The efficiency of our verifier is demonstrated using an extensive set of modular multipliers with up to several million gates.