Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
复制标题
DOI：
10.1109/tvlsi.2016.2630315
复制
发表时间：
2017-04
影响因子：
2.8
通讯作者：
R. Bishnoi;Fabian Oboril;M. Tahoori
中科院分区：
文献类型：
--
作者：
R. Bishnoi;Fabian Oboril;M. Tahoori
随着技术的缩小，静态功率已成为芯片系统中最大的挑战之一。通常，使用非挥发性（NV）顺序元素进行计算是应对这一挑战的有前途解决方案。最近，已经引入了许多NV阴影触发器架构，其中磁性隧道连接（MTJ）细胞被用作备用存储元件。由于磁层的新兴制造过程，MTJ比其CMOS对应物更容易受到制造缺陷。此外，与可以通过完善的记忆修复和编码方案有效修复的内存阵列不同，布局中散布的触发器更难修复。因此，如果没有有效的NV触发器缺陷和容错性，则制造产量将受到严重影响。在本文中，我们提出了耐故障的NV闩锁（FTNV-L）设计，其中几个MTJ单元的排列方式使其对各种MTJ断层具有弹性。仿真结果表明，我们提出的FTNV-L可以有效地忍受所有单一MTJ断层，其开销比传统方法低得多。
With technology down scaling, static power has become one of the biggest challenges in a system on chip. Normally off computing using nonvolatile (NV) sequential elements is a promising solution to address this challenge. Recently, many NV shadow flip-flop architectures have been introduced in which magnetic tunnel junction (MTJ) cells are employed as backup storing elements. Due to the emerging fabrication processes of magnetic layers, MTJs are more susceptible to manufacturing defects than their CMOS counterparts. Moreover, unlike memory arrays that can effectively be repaired with well-established memory repair and coding schemes, flip-flops scattered in the layout are more difficult to repair. Therefore, without effective defect and fault tolerance for NV flip-flops, the manufacturing yield will be affected severely. In this paper, we propose a fault-tolerant NV latch (FTNV-L) design, in which several MTJ cells are arranged in such a way that it is resilient to various MTJ faults. The simulation results show that our proposed FTNV-L can effectively tolerate all single MTJ faults with a considerably lower overhead than traditional approaches.