Robust linear sampling switch for low-voltage SAR ADCs
Robust linear sampling switch for low-voltage SAR ADCs
复制标题
适用于低压 SAR ADC 的稳健线性采样开关
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
J. Goes
中科院分区：
文献类型：
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作者：
B. Tiwari;P. Bahubalindruni;Sujay Deb;J. Goes
提出了一种工作在几十MHz频率下的低压逐次逼近寄存器(SAR)模数转换器的线性采样开关。所提出的开关采用自举传输门，其中体电压在内部产生，以最小化晶体管阈值电压随输入信号幅度的变化。因此，在低电源电压下，无需使用宽晶体管和/或电荷泵，即可在整个输入信号范围内确保几乎恒定且低的导通电阻(导通)。所提出的开关是使用标准的65纳米CMOS工艺设计的。版图后仿真结果表明，在采样频率为100 MHz，电源电压为0.8 V时，信噪比和失真比(SNDR)分别为87.81和87.81，无杂散动态范围(SFDR)和总谐波失真(THD)分别为87.81和90，总谐波失真(THD)为-91.5，HBox为-91.5。此外，在不同工艺拐角和不同温度下，该开关对输入信号幅度的最大变化量为1%，低于文献中报道的其他采样开关。
This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance ( $$R_{ON}$$ R ON ) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of $$-91.5,hbox {dB}$$ - 91.5 dB at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in $$R_{ON}$$ R ON over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.