A 500 V 1A 1-chip inverter IC with a new electric field reduction structure
A 500 V 1A 1-chip inverter IC with a new electric field reduction structure
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DOI：
10.1109/ispsd.1994.583792
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发表时间：
1994-05
期刊：
影响因子：
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通讯作者：
K. Endo;Y. Baba;Y. Udo;M. Yasui;Y. Sano
中科院分区：
文献类型：
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作者：
K. Endo;Y. Baba;Y. Udo;M. Yasui;Y. Sano
研制了一种采用新型电场抑制结构SRFP（Scroll shaped Resistive Field Plate）的500 V1 A三相逆变器集成电路。该HV-IC工艺是具有电介质隔离（DI）晶片的BiCMOS工艺。硅晶片直接键合（SDB）技术被应用到DI晶片。输出器件是具有高速集电极结构的横向IGBT。在没有SIPOS的情况下，SRFP具有与SIPOS-RFP相同的场减少效果和相同的电屏蔽效果。在这份报告中，我们表明，IGBT的关断时间取决于N/sup +/模式的集电极和周围的DI区的P/sup +/层的存在。通过优化集电极图形，实现了高速（280 nsec）和低饱和（2.8 V）电压IGBT。
A 500 V 1 A three-phase inverter IC has been developed by using a new electric field reduction structure SRFP (Scroll shaped Resistive-Field-Plate). This HV-IC process is a BiCMOS process with a dielectric isolated (DI) wafer. Si wafer direct bonding (SDB) technique is applied to the DI wafer. Output devices are lateral IGBTs with high-speed collector structures. Without SIPOS, an SRFP has the same field reduction effect and the same electric shield effect as a SIPOS-RFP. In this report, we show that turn off time of IGBT depends on N/sup +/ pattern in the collector and existence of P/sup +/ layer around the DI area. High-speed (280 nsec) and low saturation (2.8 V) voltage IGBTs are realized by using optimization of collector pattern.