YARR - A PCIe based Readout Concept for Current and Future ATLAS Pixel Modules
YARR - A PCIe based Readout Concept for Current and Future ATLAS Pixel Modules
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YARR - 适用于当前和未来 ATLAS Pixel 模块的基于 PCIe 的读出概念
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
Timon Heim
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文献类型：
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作者：
Timon Heim
YARR系统是一个DAQ系统，专为当前一代ATLAS Pixel FE-I4和下一代芯片的读出而设计。它利用商用现成的PCIe FPGA卡作为可重新配置的I/O接口，作为一个简单的网关，通过高速PCIe连接将所有数据从Pixel模块传输到主机系统的内存中。依靠现代CPU架构，它使线程中的并行处理和日常计算机中的商业高速接口的使用成为可能，可以在主机CPU中的软件级别上执行所有处理。虽然FPGA在并行信号处理方面非常强大，但它们的固件很难维护，并且受到其连接的硬件的限制。另一方面，软件是非常便携的，经常升级，新功能是免费的。不依赖底层硬件加速的DAQ概念也简化了从实验室中的原型设计到实验中的全尺寸实施的过渡。将概述总体概念和数据流，以及将处理从硬件转移到软件时可能遇到的挑战和可能的瓶颈。
The Yet Another Rapid Readout (YARR) system is a DAQ system designed for the readout of current generation ATLAS Pixel FE-I4 and next generation chips. It utilises a commercial-off-the-shelf PCIe FPGA card as a reconfigurable I/O interface, which acts as a simple gateway to pipe all data from the Pixel modules via the high speed PCIe connection into the host system’s memory. Relying on modern CPU architectures, which enables the usage of parallelised processing in threads and commercial high speed interfaces in everyday computers, it is possible to perform all processing on a software level in the host CPU. Although FPGAs are very powerful at parallel signal processing their firmware is hard to maintain and constrained by their connected hardware. Software, on the other hand, is very portable and upgraded frequently with new features coming at no cost. A DAQ concept which does not rely on the underlying hardware for acceleration also eases the transition from prototyping in the laboratory to the full scale implementation in the experiment. The overall concept and data flow will be outlined, as well as the challenges and possible bottlenecks which can be encountered when moving the processing from hardware to software.