Post-CTS clock skew scheduling with limited delay buffering
Post-CTS clock skew scheduling with limited delay buffering
复制标题
具有有限延迟缓冲的 CTS 后时钟偏差调度
DOI:
10.1109/mwscas.2009.5236113
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发表时间:
2009
期刊:
影响因子:
--
通讯作者:
B. Taskin
中科院分区:
文献类型:
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作者:
Jianchao Lu;B. Taskin
Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the leaves of the clock tree to implement a limited version of clock skew scheduling. The method suggests the limitation of delay buffering on each clock tree branch as well as a global monitoring of total amount of delay buffering to improve the circuit performance. The delay buffering for non-zero clock skew operation is performed only after the clock sinks in order to preserve the structure and the optimizations implemented with any clock tree synthesis methodology. Experimental results demonstrate the superiority of the proposed post-CTS methodology over previous methods and demonstrate an important trend of clock period improvement over varying upper bounds of delay buffering. It is shown that the majority of the clock period improvement achievable through clock skew scheduling is obtained through very limited buffering (≈43% average improvement through 10% of max buffering).