Software prefetching for indirect memory accesses
Software prefetching for indirect memory accesses
复制标题
用于间接内存访问的软件预取
DOI：
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复制
发表时间：
2017
期刊：
影响因子：
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通讯作者：
Timothy M. Jones
中科院分区：
文献类型：
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作者：
S. Ainsworth;Timothy M. Jones
许多现代数据处理和HPC工作负载都受到严重的内存延迟限制。解决这个问题的一个诱人的提议是软件预取，其中使用特殊的非阻塞加载将数据在需要之前带入该高速缓存层次结构。然而，这些很难插入以有效地提高性能，并且用于自动插入的技术目前是有限的。本文开发了一种新的编译器通过自动生成软件预取的间接内存访问，一类特殊的不规则内存访问经常出现在高性能的工作负载。我们在一系列广泛的系统中评估了这一点，所有这些系统都从该技术中受益。然后，我们评估在何种程度上良好的预取指令的架构依赖。在一组内存限制的基准测试中，我们的自动通过为Intel Haswell处理器和ARM Cortex-A57（均为无序内核）实现了1.3倍和1.1倍的平均加速，为有序ARM Cortex-A53和Intel Xeon Phi实现了2.1倍和3.7倍的性能提升。
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads are used to bring data into the cache hierarchy just before being required. However, these are difficult to insert to effectively improve performance, and techniques for automatic insertion are currently limited. This paper develops a novel compiler pass to automatically generate software prefetches for indirect memory accesses, a special class of irregular memory accesses often seen in high-performance workloads. We evaluate this across a wide set of systems, all of which gain benefit from the technique. We then evaluate the extent to which good prefetch instructions are architecture dependent. Across a set of memory-bound benchmarks, our automated pass achieves average speedups of 1.3x and 1.1x for an Intel Haswell processor and an ARM Cortex-A57, both out-of-order cores, and performance improvements of 2.1x and 3.7x for the in-order ARM Cortex-A53 and Intel Xeon Phi.
针对不规则工作负载的事件触发可编程预取器
DOI：
10.1145/3173162.3173189
发表时间：
2018
期刊：
--
影响因子：
--
作者：
Ainsworth S
通讯作者：
Ainsworth S