LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6)

LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6)
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DOI：
10.1109/ispsd.2000.856835
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发表时间：
2000-05
期刊：
12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)
影响因子：
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通讯作者：
A. Moscatelli;A. Merlini;G. Croce;P. Galbiati;C. Contiero
A. Moscatelli;A. Merlini;G. Croce;P. Galbiati;C. Contiero
中科院分区：
其他
文献类型：
--
作者：
A. Moscatelli;A. Merlini;G. Croce;P. Galbiati;C. Contiero

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This paper presents the integration approach followed to implement power LDMOS' up to 60 V into a 0.35 /spl mu/m process technology (BCD6) based on a CMOS plus Flash-Memory platform of equivalent lithography generation, built on a P-over P+ substrate. Experimental results on LDMOS' in terms of on-state specific resistance, off and on-state breakdown voltage, frequency behavior will be described analyzing the interactions between low voltage ULSI platform and high voltage power elements.