Automatic Test Pattern Generation for Interconnect Open Defects

Automatic Test Pattern Generation for Interconnect Open Defects
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自动生成互连开路缺陷的测试模式

DOI:
10.1109/vts.2008.30
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发表时间:
2008
期刊:
26th IEEE VLSI Test Symposium (vts 2008)
影响因子:
--
通讯作者:
Wu
Wu
中科院分区:
--
文献类型:
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作者:
S. Spinner;I. Polian;P. Engelke;B. Becker;Martin Keim;Wu

文献摘要

被引文献

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我们提出一个全自动流,以生成用于互连开放缺陷的测试模式。两种层间打开(通过缺陷开放)和任意的内部打开仪都可以针对目标。用于行业中使用的侵略者 - 维克特模型来描述开放缺陷的电行为。该流程使用用于参数提取(PEX)和测试生成(ATPG)的标准商业工具实施。一种高度优化的分支和结合算法来确定要分配给侵略者线的值,用于减少ATPG努力和中止的数量。所得的测试集更小,并且比在N检测测试集中的卡住覆盖率更高,并且在过程变化方面具有鲁棒性。
We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.