Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs
Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs
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3D IC 硅通孔和感应链路的带宽与面积比较
DOI：
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发表时间：
2015
期刊：
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通讯作者：
V. Pavlidis
中科院分区：
文献类型：
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作者：
I. Papistas;V. Pavlidis
三维（3-D）集成是一种有前途的技术，其可以通过垂直堆叠管芯来减轻现代IC中增加的互连长度的有害影响。已经提出了硅通孔（TSV）和AC耦合作为多个堆叠管芯之间的通信接口。本文研究了这些通信方案的3-D系统的链路带宽被视为一个约束，而不是一个目标。TSV和重分布层（RDL）的频率相关的RC模型。两种方案之间的一阶延迟分析显示出相当的性能，但TSV的面积效率更好。然而，考虑到复用方案表明，在没有复用的情况下，具有小于20 μm的间距的TSV表现出更好的带宽-面积效率，而对于12：1的复用比，与具有大于20 μm的间距的TSV相比，电感链路表现出更高的效率。
Three-dimensional (3-D) integration is a promising technology that can mitigate the deleterious effects of the increased interconnect length in modern ICs by vertically stacking dies. Through silicon vias (TSVs) and AC coupling have been proposed as communication interfaces between multiple stacked dies. This paper investigates these communication schemes for 3-D systems where the link bandwidth is treated as a constraint rather than an objective. A frequency dependent RC model for the TSV and the redistribution layer (RDL) is employed. A first order delay analysis between the two schemes shows comparable performance, but a better area efficiency for the TSV. Considering, however, a multiplexing scheme shows that TSVs with a pitch lower than 20 μm exhibit better bandwidth-to-area efficiency without multiplexing, while the inductive link demonstrates higher efficiency in comparison to TSVs with a pitch larger than 20 μm for a 12:1 multiplexing ratio.