Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins
Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins
复制标题
数字 LSI 的制造后时钟时序调整确保操作时序裕度
DOI：
10.1109/his.2008.139
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
T. Higuchi
中科院分区：
文献类型：
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作者：
T. Susa;M. Murakawa;E. Takahashi;T. Furuya;T. Higuchi
为了解决数字LSI的时钟时序波动问题（也称为“时钟偏斜”问题），我们提出了一种基于遗传算法（GA）的时钟调整方法，确保强大的时钟时序，以科普LSI环境中的波动，如温度或电源电压。该方法通过专用可调电路和调整GA软件相结合来实现，其中插入到时钟线中的多个可调延迟电路的值在制造之后由GA软件确定。实验结果表明，该方法可以提高开发的测试芯片的操作良率，同时确保足够的时间裕度。
To solve the problem of fluctuations in clock timing with digital LSIs (also known as the "clock skew" problem), we propose a genetic algorithm (GA) based clock adjustment method that ensures robust clock-timing to cope with fluctuations in the LSI environment such as temperature or power supply voltage. This method is realized by the combination of dedicated adjustable circuitry and adjustment GA software, with the values for multiple adjustable delay circuits inserted into the clock lines being determined by the GA software after fabrication. Experimental results demonstrate that the proposed method can enhance the operational yields of developed test chips while ensuring sufficient timing margins.