Delay Testing: Improving Test Quality and Avoiding Over-testing
Delay Testing: Improving Test Quality and Avoiding Over-testing
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DOI：
10.2197/ipsjtsldm.4.117
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发表时间：
2011-08
期刊：
影响因子：
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通讯作者：
S. Kajihara;S. Ohtake;T. Yoneda
中科院分区：
文献类型：
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作者：
S. Kajihara;S. Ohtake;T. Yoneda
时延测试是生产测试中保证逻辑电路高质量、高可靠性的关键环节之一。通过引入延迟测试，可以减少漏掉有缺陷芯片的测试逃逸。另一方面，我们需要关注延迟测试造成的成品率损失，即过度测试。许多方法和技术已经被用来解决延迟测试中的问题。本文介绍了时延测试的基本技术，综述了目前时延测试中存在的问题和解决方法。重点讨论了如何通过处理寄存器传输级描述的电路来提高测试质量、避免过度测试以及提高测试设计的效率。
Delay testing is one of key processes in production test to ensure high quality and high reliability for logic circuits. Test escape missing defective chips can be reduced by introducing delay testing. On the other hand, we need to concern yield loss caused by delay testing, i.e., over-testing. Many methods and techniques have been developed to solve problems on delay testing. In this paper, we introduce fundamental techniques of delay testing and survey recent problems and solutions. Especially we focus on techniques to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.