Adjustable-Cost Overlays for Runtime Compilation
Adjustable-Cost Overlays for Runtime Compilation
复制标题
用于运行时编译的可调整成本覆盖
DOI：
10.1109/fccm.2015.49
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
G. Stitt
中科院分区：
文献类型：
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作者：
J. Coole;G. Stitt
以前的工作已经表明，虚拟架构，或覆盖，可以大大减少冗长的FPGA编译时间，提供应用程序专用的资源沿着灵活的互连，以支持应用程序的变化。然而，保持互连的完全可配置性还需要显著的面积开销。在本文中，我们介绍了一个家庭的覆盖架构称为超网和相关的设计方法，使用数据路径合并提供最小的开销支持多个源网络列表，并可选地提供了一个可调的源的灵活性，通过二级互连网络。我们证明，超级网可以使运行时编译速度高达13,000倍，比直接寄存器传输逻辑（RTL）的实现，与选择性启用RTL数据路径的面积减少70%。最后，我们探讨了这个家庭的覆盖的设计空间，并表明它提供了显着的自由，以增加灵活性，以支持从源集的偏差，在开发过程中或在运行时进行的优化交易的额外区域。
Previous work has shown that virtual architectures, or overlays, can greatly reduce lengthy FPGA compile times by providing application-specialized resources along with a flexible interconnect to support application changes. However, retaining full configurability of interconnect has also required significant area overhead. In this paper, we introduce a family of overlay architectures called super nets and an associated design methodology that uses data path merging to provide minimal-overhead support for multiple source net lists, and optionally provides an adjustable amount of source flexibility through a secondary interconnect network. We demonstrate that super nets can enable runtime compilation up to 13,000× faster than direct register-transfer logic (RTL) implementation, with up to 70% lower area than selectively enabled RTL data paths. Finally, we explore the design space of this family of overlays and show that it affords significant freedom to trade additional area for increased flexibility to support deviations from the source set, as introduced during development or by optimizations performed at runtime.