A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits
复制标题
使用二进制控制差分对电路的多值可重构VLSI架构
DOI：
10.1587/transele.e96.c.1083
复制
发表时间：
2013
期刊：
影响因子：
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通讯作者：
M. Kameyama
中科院分区：
文献类型：
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作者：
Xu Bai;M. Kameyama
本文提出了一种使用多值开关块和二进制逻辑模块的细粒度位串行可重构VLSI结构。利用多值信令来实现紧凑的开关块。介绍了一种二进制控制的电流舵技术，利用可编程三电平差分对电路实现高性能、低功耗的任意二进制函数，与四进制控制的差分对电路相比，提高了噪声容限。提出了一种在串联门控差分对电路和电流模式D锁存器之间共享电流源的技术，以减少电流源的数量，提高速度。它表明，所提出的多值单元的二进制控制的电流舵技术和电流源共享技术的基础上的功耗和延迟降低到63%和72%，分别与以前的多值单元相比。关键词：细粒度可重构VLSI结构，多值开关块，二进制控制电流舵技术，电流源共享技术，电流模式逻辑
This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell. key words: fine-grain reconfigurable VLSI architecture, multiple-valued switch block, binary-controlled current-steering technique, current-source sharing technique, current-mode logic (CML)