Clock-gating and its application to low power design of sequential circuits
Clock-gating and its application to low power design of sequential circuits
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DOI：
10.1109/cicc.1997.606671
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发表时间：
1997-05
期刊：
影响因子：
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通讯作者：
Qing Wu;Massoud Pedram;Xunwei Wu
中科院分区：
文献类型：
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作者：
Qing Wu;Massoud Pedram;Xunwei Wu
本文用一个四元变量来描述时序电路中的时钟行为，并利用这种表示方法提出和分析了两种时钟门控技术。然后，它使用时钟的触发转换和各种触发器的有效周期之间的覆盖关系，以生成电路中的每个触发器的派生时钟。接下来提供使用门控时钟的设计示例。实验结果表明，这些设计具有理想的逻辑功能，与传统的设计相比，具有较低的功耗。
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock gating techniques. It then uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a derived clock for each flip-flop in the circuit. Design examples using gated clocks are provided next. Experimental results show that these designs have ideal logic functionality with lower power dissipation compared to traditional designs.