Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS
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DOI:
10.1109/tie.2015.2500187
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发表时间:
2016-04
影响因子:
7.7
通讯作者:
Ji Hu;O. Alatise;J. González;R. Bonyadi;P. Alexakis;L. Ran;P. Mawby
Ji Hu;O. Alatise;J. González;R. Bonyadi;P. Alexakis;L. Ran;P. Mawby
中科院分区:
计算机科学1区
文献类型:
--
作者:
Ji Hu;O. Alatise;J. González;R. Bonyadi;P. Alexakis;L. Ran;P. Mawby

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并联设备之间的热和电开关时间常数的差异会导致功率和温度分布不平衡,从而降低模块的稳健性。本文研究了在钳位电感开关(CIS)和非钳位电感开关(UIS)下,并联器件之间的电热变化(栅极和热阻)对900V-CoolMOS和1.2KV-SiCMOSFET模块稳健性的影响。在CIS下,对于给定的栅极和热阻差(ΔRG和ΔRTH),并联器件之间的稳态结温度(ΔTJ)和开关能量(ΔESw)的差被用作衡量标准,以确定器件对电热变化的稳健性,即器件在使用不同的速率和热阻开关的情况下保持均匀温度激励的程度。在UIS条件下,使用作为并联设备之间的ΔTJ和ΔRG的函数的设备故障前的最大雪崩电流/能量的变化作为度量。在CIS和UIS两种情况下,SIC器件都表现出更好的性能,并且对并联器件之间的电热变化的负面响应最小。还建立了有限元模型,显示了在不同技术条件下,BJT闭锁的动态情况。
Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature (ΔTJ) and switching energy (ΔESW) between the parallel-connected devices for a given difference in the gate and thermal resistance (ΔRG and ΔRTH) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ΔTJ and ΔRG between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.